1. Field of the Invention
The present invention relates to a static semiconductor memory device (hereinafter, referred to as xe2x80x9cSRAM (Static Random Access Memory)xe2x80x9d), and more particularly to a memory cell structure of a CMOSSRAM.
2. Description of the Background Art
FIG. 14 shows the conventional layout configuration of a non-load SRAM memory cell formed from four tansistors. FIG. 12 is an equivalent circuit diagram of FIG. 14.
The SRAMs of this type are described in, for example, xe2x80x9cA 1.9-xcexcm2 Loadless CMOS Four-Transistor SRAM Cell In a 0.18-xcexcm Logic Tecnologyxe2x80x9d, international journal IEDM ""98, pp. 643-646 and xe2x80x9cAn Ultrahigh-Density High-Speed Load less Four-Tristor SRAM Macro with Twisted Bit Line Architecture and Triple-Well Shieldxe2x80x9d, international journal IEEE JSSC VOL. 36, No. 3, March 2001.
As shown in FIG. 14, a memory cell 1 includes four MOS (Metal Oxide Semiconductor) transistors. Specifically, memory cell 1 includes NMOS transistors N1 and N2 in a P well and PMOS transistors P1 and P2 in an N well.
NMOS transistor N1 is located at an intersection between an N-type diffusion region 2a and a polysilicon wiring 3c, and NMOS transistor N2 is located at an intersection between an N-type diffusion region 2b and a polysilicon wiring 3b. PMOS transistor P1 is located at an intersection between a P-type diffusion region 2c and a polysilicon wiring 3a, and PMOS transistor P2 is located at an intersection between a P-type diffusion region 2d and a polysilicon wiring 3a. 
PMOS transistors P1 and P2 are access transistors and NMOS transistors N1 and N2 are driver transistors. Diffusion regions 2a to 2d are connected to upper layer wirings through contact holes 4a to 4h, respectively.
With the layout configuration shown in FIG. 14, a word line WL is arranged in a lateral direction while bit line pairs BL1 and BL2 are arranged in a longitudinal direction. As shown in FIG. 14, the layout configuration of one bit is long in the longitudinal direction and a bit line, therefore, becomes long in this configuration. In addition, high resistance polysilicon wirings 3b and 3c are present on the path (path for pulling out bit lines) between a bit line and a GND line.
As described above, since the conventional four-transistor SRAM memory cell is long in a bit line direction, the wiring capacitance of each bit line is high. Due to this, access time is slow. Further, since high resistance polysilicon wirings 3b and 3c are present on the paths between bit line contact sections (contact holes 4f and 4h) and ground contact sections (contact holes 4a and 4c), respectively, the resistance of each path is high. The high resistance of the path also causes a delay in access time, disadvantageously hampering increasing the see of the SRAM.
Furthermore, the direction of the gates and diffusion regions of access transistor and P2 differ from that of the gates and diffusion regions of driver transistors N1 and N2. Due to this, variations in the widths and positions of formation patterns for gates or the like become large after photolithographic processing. If variations in gate width and the like become large, the characteristics of the respective tranistors disadvantageously change.
Moreover, if the position at which polysilicon wiring 3c is formed is deviated horizontally, for example, in FIG. 14, a short circuit is generated between polysiicon wiring 3c and contact hole 4a or 4b. If the position at which polysilicon wiring 3a is formed is deviated vertically, for example, in FIG. 14, a shortcuit is generated between polysilicon wiring 3a and contact holes 4e to 4h. As can be seen, even if a gate pattern is deviated either vertically or horizontally, a short-circuit may possibly be generated between the polysilicon wiring and the contact hole which should be separated from each other, making it disadvantageously difficult to secure a margin for manufacturing irregularities caused by a mask error or the like.
The present invention has been achieved to solve the above described disadvantages. It is an object of the present invention to accelerate an SRAM and to secure a manufacturing irregularity margin.
According to one aspect of the present invention, a static semiconductor memory device includes: first and second bit lines; a word line; first and second access MOS transistors of a first conductive type, having sources connected to the first and second bit lines, respectively, and having gates connected to the word line in common; and first and second driver MOS transistors of a second conductive type different from the first conductive type, having sources applied with a ground potential, having drains connected to drains of the first and second access MOS transistors, respectively, and having gates connected to the drains of the second and first access MOS transistors, respectively. The drain of the first access MOS transistor is connected to the drain of the first driver MOS transistor by using a metal wiring without interposing a gate of the second driver MOS transistor therebetween, and the drain of the second access MOS transistor is connected to the drain of the second driver MOS transistor by using a metal wiring without interposing a gate of the first driver MOS transistor therebetween.
As can be seen, an access MOS transistor is connected to each driver MOS transistor by using a metal wiring lower in r than an ordinary gate without interposing the gate of the other driver MOS transistor therebetween. It is, therefore, possible to decrease the resistance between the bit line and the ground line. It is thereby possible to accelerate an SRAM.
According to another aspect of the present invention, a static semiconductor memory device includes: first and second access MOS tranistors of a second conductive type, formed on a first well of a first conductive type; first and second driver MOS transistors of the first conductive type, formed on a second well of the second conductive type; a word line connected to gates of the first and second access MOS transistors, and extending in a direction in which the first and second wells are aligned; and first and second bit lines connected to sources of the first and second access MOS transistors, respectively, and extending in a direction perpendicular to the direction in which the first and second wells are aligned First and second diffusion regions of the second conductive type for forming sources and drains of the first and second access MOS transistors are extended in a same direction as a direction in which third and fourth diffusion regions of the first conductive type for forming sources and drains of the first and second driver MOS transistors are extended, gates of the first and second access MOS transistors are extended in a same direction as a direction in which gates of the first and second driver MOS transistors are extended, and the drains of the first and second access MOS transistors are connected to the drains of the first and second driver MOS transistors by using first and second metal wirings without interposing the gates of the first and second driver MOS tranistors therebetween, respectively.
As described above, by connecting the drain of an access MOS transistor to the drain of a driver MOS transistor by using a metal wiring without interposing the gate of the driver MOS tansistors therebetween, it is possible to avoid interposing a polysilicon wiring on the path between these drains. It is thereby possible to decrease the resistance of the path. In addition, since the bit lines are extended in the direction perpendicular to the direction in which the first and second wells are aligned, it is possible to reduce the length of each bit line. Further, since the first, second, third and fourth diffusion regions (active regions) are extended in the same direction and the gate of an access MOS transactor is extended in the same direction in which the gate of a driver MOS transistor is extended it is possible to decrease vacations in the width and positions of formation patterns for gates or the like after photolithography. Besides, even if each gate is deviated in the extension direction longitudinal direction) thereof, it is possible to avoid short-circuits between the gate and the contact holes provided on the both sides thereof in the width direction. That is, it is possible to allow the gate to be shifted in the longitudinal direction to some extent.
It is preferable to provide a fist contact section reaching the gate of the first driver MOS transistor and the drain of the second driver MOS transistor, and to provide a second contact section reaching the gate of the second driver MOS transistor and the drain of the first driver MOS transistor. That is, it is preferable to provide shared contact sections between the gates and drains of the driver MOS transistors.
The first and second access MOS transistors may be arranged to be aligned in the direction in which the word line is extended. In addition, the second metal wiring may be formed from a metal wiring on a layer above the first metal wiring.
It is preferable that an area of each of the drains of the first and second driver MOS transistors is made smaller than an area of each of the sources of the first and second driver MOS transistors. For example, if an SRAM includes first and second wirings for forming the gates of the first and second driver MOS transistors, the gates of the first and second driver MOS tranistors may be arranged on the drain side of the first and second driver MOS transistors by bending the first and second wirings.
It is preferable that a gate length of each of the first and second driver MOS transistors is made longer than a gate length of each of the first and second access MOS transistors. For example, if an SRAM includes first and second wirings for forming the gates of the first and second driver MOS tansistors, a gate length of each of the first and second driver MOS trans s can be made longer than a gate length of each of the first and second access MOS transistors by locally expanding widths of the first and second wiring.
According to still another aspect of the present invention, a static semiconductor memory device includes: a first well of a second conductive type, formed between second and third wells of a first conductive type; first and second access MOS transistors of the second conductive type, formed on the second well; first and second driver MOS transistors of the first conductive type, formed on the first well; third and fourth access MOS transistors of the second conductive type, formed on the third well; a first word line connected to gates of the first and second access MOS transistors, and extending in a direction in which the first, second and third wells are aligned; a second word line connected to gates of the third and fourth access MOS transistors, and extending in the direction in which the first, second and third wells are aligned; first and second bit lines connected to sources of the first and second access MOS transistors, respectively, and extending in a direction perpendicular to the direction in which the first, second and third wells are aligned; and third and fourth bit lines connected to sources of the third and fourth access MOS transistors, respectively, and extending: in the direction perpendicular to the direction in which the first, second and third wells are aligned. First, second, third and fourth diffusion regions of the second conductive type, for forming the sources and drains of the first, second, third and fourth access MOS tansistors are extended in the same direction as a direction in which fifth and sixth diffusion regions of the first conductive type, for forming sources and drains of the first and second driver MOS transistors are extended, the gates of the first, second, third and fourth access MOS transistors are extended in the same direction as a direction in which gates of the first and second driver MOS transistors are extended, and the drains of the first, second, third and fourth access MOS transistors are connected to the drains of the first and second driver MOS transistors by using first and second metal wirings without interposing the gates of the first and second driver MOS tranistors therebetween, respectively.
Even in case of such an SRAM including 2-port memory cells according to this aspect, the drain of an access MOS transistor is connected to the drain of a driver MOS transistor by using a metal wiring without interposing the gate of the driver MOS transistor therebetween It is, therefore, possible to avoid interposing a polysilicon wiring on a path between these drains and to decrease the resistance of the path. In addition, since the bit lines are extended in the direction perpendicular to the direction in which the first to third wells are aligned, it is possible to reduce the length of each bit line. Further, since the first to sixth diffusion regions (active regions) are extended in the same direction and the gate of an access MOS transistor is extended in the same direction in which the gate of a driver MOS transistor is extended, it is possible to decrease variations in the width and positions of formation patterns for gates or the like after photolithography. Besides, it is possible to allow the gate to be shifted in the longitudinal direction to some extent.
It is preferable that the first and second bit lines are formed on the second well, and that the third and fourth bit lines are formed on the third well.